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1. features ? sensitive layer over a 0.35 m cmos array image zone: 0.4 x 14 mm = 0.02" x 0.55" image array: 8 x 280 = 2240 pixels pixel pitch: 50 m x 50 m = 500 dpi pixel clock: up to 2 mhz enabli ng up to 1780 frames per second die size: 1.64 x 17.46 mm operating voltage: 3v to 3.6v naturally protected against esd: > 16 kv air discharge power consumption: 16 mw at 3.3v, 1 mhz, 25c operating temperature range: -40c to +85c chip-on-board (cob), chip-on- board (cob) with connector complies with the european directive fo r restriction of hazardous substances (rohs directive) 2. applications pda (access control, data protection) notebook, pc-add on (access control, e-business) pin code replacement automated teller machines, pos building access electronic keys (cars, home) portable fingerprint imaging for law enforcement tv access figure 2-1. fingerchip ? packages chip-on-board package with connector chip-on-board package (cob) actual size thermal fingerprint sensor with 0.4 mm x 14 mm (0.02" x 0.55") sensing area and digital output (on-chip adc) at77c102b fingerchip ? rev. 5364a?biom?09/05
2 5364a?biom?09/05 at77c102b the die attach is connected to pins 1, 7 and 21, and must be grounded. the fpl pin must be grounded. table 2-1. pin description for chip-on-board package: at77c102b-cb01yv pin number name type 1gndgnd 2 ave analog output 3 avo analog output 4tpppower 5 tpe digital input 6vccpower 7gndgnd 8 rst digital input 9 pclk digital input 10 oe digital input 11 ackn digital output 12 de0 digital output 13 do0 digital output 14 de1 digital output 15 do1 digital output 16 de2 digital output 17 do2 digital output 18 de3 digital output 19 do3 digital output 20 fpl gnd 21 gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 gnd ave avo tpp tpe vcc gnd rst pclk oe ackn de0 do0 de1 do1 de2 do2 de3 do3 fpl gnd
3 5364a?biom?09/05 at77c102b note: 1. ref. connector: fh18-21s-0.3shw (hirose). table 2-2. pin description for cob with connector package: at77c102b-cb02yv (1) pin number name type 1fplgnd 2 not connected 3 not connected 4 de3 digital output 5 do3 digital output 6 de2 digital output 7 do2 digital output 8 de1 digital output 9 do1 digital output 10 de0 digital output 11 do0 digital output 12 ave analog output 13 avo analog output 14 tpp power 15 tpe digital input 16 vcc power 17 gnd gnd 18 rst digital input 19 pclk digital input 20 oe digital input 21 ackn digital output
4 5364a?biom?09/05 at77c102b figure 2-2. cob with flex (1) figure 2-3. flex output side note: 1. flex is not provided by atmel. flex with metallizations up flex with metallizations down 2 3 1 flex output (fingerchip connector side) metallizations up
5 5364a?biom?09/05 at77c102b 3. description the at77c102b is part of the atmel fingerchip monolithic fingerprint sensor family for which no optics, no prism and no light source are required. the at77c102b is a single-chip, high-performance, low-cost sensor based on temperature physical effects for fingerprint sensing. the at77c102b has a linear shape, which captures a fingerprint image by sweeping the finger across the sensing area. after capturing several images, atmel proprietary software can recon- struct a full 8-bit fingerprint image. the at77c102b has a small surface combined with cmos technology, and a chip-on-board package assembly. these facts contribute to a low-cost device. the device delivers a programmable number of images per second, while an integrated analog- to-digital converter deliv ers a digital signal adapted to interf aces such as an epp parallel port, a usb microcontroller or directly to microprocessor s. no frame grabber or glue interface is there- fore necessary to send the frames. these fact s make at77c102b an easy device to include in any system for identification or verification applications. table 3-1. absolute maximum ratings () parameter symbol comments value positive supply voltage v cc gnd to 4.6 note: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this s pecification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. temperature stabilization power tpp gnd to 4.6 front plane fpl gnd to v cc +0.5 digital input voltage rst pclk gnd to v cc +0.5 storage temperature t stg -50 to +95 lead temperature (soldering, 10 seconds) t leads do not solder forbidden table 3-2. recommended conditions of use parameter symbol comments min typ max unit positive supply voltage v cc 3v 3.3v 3.6v v front plane fpl must be grounded gnd v digital input voltage cmos levels v digital output voltage cmos levels v digital load c l 50 pf analog load c a r a not connected pf k ? operating temperature range t amb v grade -40 c to +85 cc maximum current on tpp itpp 0 100 ma
6 5364a?biom?09/05 at77c102b table 3-3. resistance parameter min valu e standard method esd on pins. hbm (human body model) cm os i/o 2 kv mil-std-883 - method 3015.7 on die surface (zapgun) air discharge 16 kv nf en 6100-4-2 mechanical abrasion number of cycles without lubricant multiply by an estimated factor of 20 for correlation with a real finger 200 000 mil e 12397b chemical resistance cleaning agent, acid, grease, alcohol, diluted acetone 4 hours internal method table 3-4. specifications explanation of test levels i 100% production tested at +25c ii 100% production tested at +25c, and sample tested at specified temperatures (ac testing done on sample) iii sample tested only iv parameter is guaranteed by design and/or characterization testing v parameter is a typical value only vi 100% production tested at temperature extremes d 100% probe tested on wafer at t amb = +25c table 3-5. physical parameter parameter test level min typ max unit resolution iv 50 m size iv 8 x 280 pixel yield: number of bad pixels i 5 bad pixels equivalent resistance on tpp pin i 20 30 47 ?
7 5364a?biom?09/05 at77c102b . note: 1. with i ol = 1 ma and i oh = -1 ma table 3-6. 3.3v power supply the following characteristics are applicable to the operating temperature -40 c ta +85 c typical conditions are: v cc = +3.3 v; t amb = 25c; f pclk = 1 mhz; duty cycle = 50% c load 120 pf on digital outputs, analog outputs disconnected unless otherwise specified parameter symbol test level min typ max unit power requirements positive supply voltage v cc 3.0 3.3 3.6 v active current on v cc pin, 1 mhz current on v cc pin, in static mode c load = 0 pf i cc i iv 5 4 7 5 ma ma power dissipation on v cc c load = 0 p cc i iv 16 13 25 18 mw mw current on v cc in nap mode i ccnap i10a analog output voltage range v avx iv 0 2.9 v digital inputs logic compatibility cmos logic ?0? voltage v il i0 0.8v logic ?1? voltage v ih i2.3 vccv logic ?0? current i il i-10 0a logic ?1?current i ih i 0 10 a tpe logic ?0? voltage i il tpe 1 -10 0 a tpe logic ?1? voltage i ih tpe 1 0 300 a digital outputs logic compatibility cmos logic ?0? voltage (1) v ol i0.6v logic ?1? voltage (1) v oh i2.4 v
8 5364a?biom?09/05 at77c102b . figure 3-1. reset table 3-7. switching performances the following characteristics are applicable to the operating temperature -40 c ta +85 c typical conditions are: nominal voltage; t amb = 25 c; f pclk = 1 mhz; duty cycle = 50% c load 120 pf on digital and analog outputs unless otherwise specified parameter symbol test level min typ max unit clock frequency f pclk i0.512mhz clock pulse width (high) t hclk i 250 ns clock pulse width (low) t lclk i 250 ns clock setup time (high)/reset falling edge t setup i0ns no data change t nooe iv 100 ns reset pulse width high t hrst iv 50 ns table 3-8. 3.3v 10% power supply parameter symbol test level min typ max unit output delay from pclk to ackn rising edge t plhackn i 145 ns output delay from pclk to ackn falling edge t phlackn i 145 ns output delay from pclk to data output dxi t pdata i 120 ns output delay from pclk to analog output avx t pav i d e o i 250 ns output delay from oe to data high-z t dataz iv 34 ns output delay from oe to data output t zdata iv 47 ns t hrst t setup reset rst clock pclk
9 5364a?biom?09/05 at77c102b figure 3-2. read one byte/two pixels figure 3-3. output enable t pdata clock pclk f pclk t hclk t lclk t plhackn t phlackn t pavideo acknowledge ackn data output do0-3, de0-3 video analog output avo, ave data #n+1 data #n data #n-1 data #n+2 data #n+1 data #n hi-z hi-z output enable oe data output do0 -3, de0 -3 data output t zdata t dataz
10 5364a?biom?09/05 at77c102b figure 3-4. no data change note: oe must not change during tnooe after the pclk falls. this is to ensure that the output dr ivers of the data are not drivin g cur- rent, so as to reduce the noise level on the power supply. figure 3-5. at77c102b block diagram 3.1 functional description the circuit is divided into two main sections: sensor and data conversion. one particular column among 280 plus one is selected in the sensor array (1), then each pixel of the selected column sends its electrical information to the amplifiers (2) [one per line], then two lines at a time are selected (odd and even) so that two particular pixels send their information to the input of two 4- bit analog-to-digital converters (3), so two pixels can be read for each clock pulse (4). pclk t nooe oe 2240 8 latches chip temperature sensor line sel odd ev en 8 lines of 280 columns of pixels 4-bit adc adc 8 1 dummy colum n 4 4 am p chip temperature stabilizati on ackn de0-3 do0-3 output enable analog output oe ave avo tpe tpp 1 8 pclk rst clock reset column selection 4-bit
11 5364a?biom?09/05 at77c102b figure 3-6. functional description 3.2 sensor each pixel is a sensor in itself. the sensor detects a temperature difference between the begin- ning of an acquisition and the reading of the information: this is the integration time. the integration time begins with a reset of the pixel to a predefined initial state. note that the integra- tion time reset has nothing to do with the reset of the digital section. then, at a rate depending on the sensitivity of the pyroelectric layer, on the temperature varia- tion between the reset and the end of the integration time, and for the duration of the integration time, electrical charges are generated at the pixel level. 3.3 analog-to-digital converter/ reco nstructing an 8-bit fingerprint image an analog-to-digital converter (adc) is used to convert the analog signal coming from the pixel into digital data that can be used by a processor. as the data rate for the parallel port and the usb is in the range of 1 mb per second, and at least a rate of 500 frames per second is needed to reconstruct the image with a fair sweeping speed of the finger, two 4-bit adcs have been used to output two pixels at a time on one byte. 3.4 start sequence a reset is not necessary between each frame acquisition. the start sequence must consist in: 1. setting the rst pin to high. 2. setting the rst pin to low. 3. sending 4 clock pulses (due to pipe-line). 4. sending clock pulses to skip the first frame. note that after a reset it is re commended to skip the fi rst 200 slices to st abilize the acquisition. figure 3-7. start sequence 8 latches chip temperature sensor column selection line sel odd ev en 8 lines of 280 columns of pixels 4-bit adc adc 8 1 dummy colum n 4 4 am p de0-3 do0-3 1 2 3 4 4-bit 1 4 3 1 2 1 1124 clock pclk reset rs t 4 + 1124 clock pulses to skip the first fram e
12 5364a?biom?09/05 at77c102b 3.5 reading the frames a frame consists of 280 true columns plus one dummy column of eight pixels. as two pixels are output at a time, a system must send 281 x 4 = 1124 clock pulses to read one frame. reset must be low wh en reading the frames. 3.6 read one byte/output enable the clock is taken into account on its falling edge and data is output on its rising edge. for each clock pulse, after the start sequence, a new byte is output on the do0-3 and de0-3 pins. this byte contains two pixels: 4-bit on do0-3 (odd pixels), 4-bit on de0-3 (even pixels). to output the data, the output enable (oe) pin must be low. when oe is high, the do0-3 and de0-3 pins are in high-impedance state. this facilitates an easy connection to a microprocessor bus without additional circuitry since the data output can be enabled using a chip select signal. note that the at77c102b always sends data: there is no data exchange to switch to read/write mode. 3.7 power supply noise important: when a falling edge is applied on oe (that is when the output enable becomes active), then some current is drained from the power supply to drive the eight outputs, producing some noise. it is important to av oid such noise just after the pc lk clock?s falling edge, when the pixels? information is evaluated: the timing diagram ( figure 3-2 ) and time t nooe define the inter- val time when the power supply must be as quiet as possible. 3.8 video output an analog signal is also availa ble on pins ave and avo. note that video output is available one clock pulse before the corresponding digital outpu t (one clock pipe-line delay for the analog to digital conversion). 3.9 pixel order after a reset, pixel 1 is located on the upper left corner, looking at the chip with bond pads to the right. for each column of eight pixels, pixels 1, 3, 5 and 7 are output on odd data do0-3 pins, and pixels 2, 4, 6 and 8 are output on even data de0-3 pins. the most significant bit (msb) is bit 3, and the least significant bit is bit 0. figure 3-8. pixel order b ond p ads pixel #1 (1,1) pixel #2233 (280,1) pixel #8 (1,8) pixel #2240 (280,8)
13 5364a?biom?09/05 at77c102b 3.10 synchronization: the dummy column a dummy column has been added to the sensor to act as a specific pattern to detect the first pixel. therefore, 280 true columns plus one dummy column are read for each frame. the four bytes of the dummy column contain a fixed pattern on the first two bytes, and tempera- ture information on the last two bytes. note: x represents 0 or 1 the sequence 111x0000 111x0000 appears on ev ery frame (exactly every 1124 clock pulses), so it is an easy pattern to reco gnize for synchronization purposes. 3.11 thermometer the dummy bytes db3 and db4 contain some internal temperature information. the even nibble nnnn in db3 can be used to measure an increase or decrease of the chip?s tem- perature, using the difference between two measures of the same physical device. the following table gives values in kelvin. table 1. dummy column description dummy byte odd even dummy byte 1 db1: 111x 0000 dummy byte 2 db2: 111x 0000 dummy byte 3 db3: rrrr nnnn dummy byte 4 db4: tttt pppp table 1. temperature table nnnn decimal nnnn binary temperature differential with code 8 in kelvin 15 1111 > 11.2 14 1110 8.4 13 1101 7 12 1100 5.6 11 1011 4.2 10 1010 2.8 9 1001 1.4 8 1000 0 7 0111 -1.4 6 0110 -2.8 5 0101 -4.2 4 0100 -5.6 3 0011 -7 2 0010 -8.4 1 0001 -11.2 0 0000 < -16.8
14 5364a?biom?09/05 at77c102b for code 0 and 15, the absolute va lue is a minimum (saturation). when the image contrast becomes faint because of a low temperature difference between the finger and the sensor, it is recommended to use the temperat ure stabilization circuitry to increase the temperature by two codes (that is from 8 to 10), so as to obtain a sensor increase of at least >1.4 kelvin. this enables enough contrast to obtain a proper fingerprint reconstruction. 3.12 integration ti me and clock jitter the at77c102b is not very sensitive to clock jit ters (clock variations). the most important requirement is a regular integration time that ensures the frame reading rate is also as regular as possible, so as to obtain consistent fingerprint slices. if the integration time is not regular, the contrast can vary from one frame to another. note that it is possible to introduce some waiting time between each set of 1124 clock pulses, but the overall time of one frame read must be regular. this waiting time is generally the time needed by the processor to perform some calculation over the frame (to detect the finger, for instance). figure 3-9. read one frame figure 3-10. regular integration time 3.13 power management 3.14 nap mode several strategies are possible to reduce power consumption when the device is not in use. the simplest and most efficient is to cut the power supply using external means. a nap mode is also implemented in the at77c102b. to activate this nap mode, you must: 1. set the reset rst pin to high. by doing this, all analog sections of the device are inter- nally powered down. 2. set the clock pclk pin to high (or low), thus stopping the entire digital section. 3. set the tpe pin to low to stop the temperature st abilization feature. 4. set the output enable oe pin to high, so that the output is forced in hiz. clock pclk reset rst is lo w 123456 1124 1123 1122 1121 1120 1119 column 1 column 2 column 280 dummy column 281 pixels 1 & 2 3 & 4 5 & 6 7 & 8 1 & 2 3 & 4 7 & 8 db1 db2 db3 db 4 clock pclk regular integration time fram e n 1124 pulses fram e n+1 1124 pulses fram e n+2 1124 pulses fram e n+3 1124 pulse s
15 5364a?biom?09/05 at77c102b figure 3-11. nap mode in nap mode, all internal transistors are in shut mode. only leakage current is drained in the power supply, generally less than the tested value. 3.15 static current consumption when the clock is stopped (set to 1) and the reset is low (set to 0), the device?s analog sections drain some current, whereas, if the outputs are connected to a standard cmos input, the digital section does not consume any current (no current is drained in the i/o). in this case the typical current value is 5 ma. this current does not depend on the voltage (it is almost the same from 3 to 3.6v). 3.16 dynamic current consumption when the clock is running, the digital sections, and particularly the outputs if they are heavily loaded, consume current. in any case, the current should be less than the testing machine (120 pf load on each i/o), and a maximum of 50 pf is recommended. the at77c102b, running at about 1 mhz, consumes less than 7 ma on the v cc pin. 3.17 temperature stabilization power consumption (tpp pin) when the tpe pin is set to 1, current is drained via the tpp pin. the current is limited by the internal equivalent resistance given in table 3-4 on page 6 and a possible external resistor. most of the time, tpe is set to 0 and no current is drained in tpp. when the image contrast becomes low because of a low temperature different ial (less than 1 kelvin), then it is recom- mended to set tpe to 1 for a short time so that the dissipated power in the chip elevates the temperature, allowing contrast recovery. the necessary time to increase the chip?s temperature by one kelvin depends on the dissipated power, the thermal capacity of the silicon sensor and the thermal resistance between the sensor and its surroundings. as a rule of thumb, dissipating 300 mw in the chip elevates the temperature by 1 kelvin in one second. with the 30 ? typical value, 300 mw is 3v applied on tpp. if the power supply is 3.6v, an external resistor must be added in the application to limit the current under 100 ma. nap clock pclk reset rs t nap mode
16 5364a?biom?09/05 at77c102b 4. packaging: mechanical data figure 4-1. product reference: at77c102b-cb01yv figure 4-2. product reference: at77c102b-cb01yv 1 26.6 0.3 side view scale 10/1 0.74 0.06 top view scale 10/1 0.89 0.3 0.32 2.33 0.5 1.64 +0.07 -0.01 9 0.3 max 0.2 5.20 0.2 max 0.82 0.18 max. dam and fill 0.82 0.50 max 2.95 0.50 5.90 top view (all dimensions in mm) 4 b 1.5 a at 0.4 heigh from b ref. min 0.2 a bottom view (all dimensions in mm) 1 0.08 0.5 0.1 0.08 3.5 0.08 1 0.15 2 0.08 0.08 1.5 2 0.15 0.1 23.85 ro. 75 +0.08 -0.12 (x3) 1.5 +0.15 - 0.23 (x3) 0.75 +0.33 - 0.25 6.30 2.15 0.15 1.15 0.15 + _ + _ + _ + _ + _ + _ + _ + _ + _ + _ + _
17 5364a?biom?09/05 at77c102b figure 4-3. product reference: at77c102b-cb02yv 4.1 package information 4.1.1 electrical disturbances when looking at the fingerchip device from the top with the glob top to the right, the right edge must never be in contact with customer casing or any component to avoid electrical disturbances. figure 4-4. epoxy overflow maximum epoxy overflow width: 0.55 mm on the die edge. maximum epoxy overflow thickness: 0.33 mm. note: refer to figure 4-1 on page 16 . flex output 26.6 0.3 8.8 0.2 a a 5.2 max 2.39 0.5 0.74 0.06 4.1 0.5 8.9 0.5 r0.75 + 0.08 -0.12 1.78 0.5 1.25 0.5 14.32 +0.04 -0.01 6.3 0.1 1.5 +0.15 -0.23 (x 0.75 +0.33 -0.25 1.64 +0.07 -0.01 5.9 max 4.1 0.2 2.9 0.5 1.5 max 1.9 0 . 4 0.2 min 0.82 0.18 scale 4/1 all dimensions in mm flex output 9.85 0.3 + _ 3 ) (x 3) (x 2) 0.55 0.33 fingerchip epoxy glue overflow aa section
18 5364a?biom?09/05 at77c102b 5. ordering information 5.1 package device at77c 102b- ? atmel prefix temperature range v: -40 c to +85 o c quality level: ? : standard package cb01: chip on board (cob) cb02: cob with connector cbxx fingerchip family device type v y rohs compliant o
printed on recycled paper. 5364a?biom?09/05 ? atmel corporation 2005 . all rights reserved. atmel ? , logo and combinations thereof, everywhere you are ? , fingerchp ? and others, are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. ddisclaimer: the information in this document is provided in connection with atmel products. no license, expr ess or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel? s web site, atmel assumes no liability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to , the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, conseque ntial, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if at mel has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the ri ght to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications intended to support or sustain life. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131, usa tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906, usa tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imagin g/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 literature requests www.atmel.com/literature

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